1. Field of the Invention
The present invention relates to an FET gate bias circuit having a Schottky barrier gate incorporated therein, and more particularly, to a gate bias circuit for a GaAs FET amplifier used in the range from submicrowave band to microwave band.
2. Description of the Related Art
With recent development of higher-output GaAs FETs, an FET package capable of providing saturation output power of 30 watts or more has been made practicable and is used in radio equipment for mobile communications using the submicrowave band (1-3 GHz) or in a multiplex radio device, satellite base station, etc. using the microwave band. The present invention relates to an FET gate bias circuit for holding the bias voltage applied to the gate of a GaAs FET at a constant value regardless of the output power, thereby suppressing variations in the drain current of the GaAs FET.
A conventional GaAs FET gate bias circuit will be explained with reference to FIG. 8, which is a circuit diagram of an amplifier using a GaAs FET.
A high-output GaAs FET is generally used as shown in the circuit diagram of FIG. 8. Specifically, the source (S) of a GaAs FET Q1 is grounded, a positive voltage is applied to a terminal 1 so that a positive bias voltage is applied to the drain (D), and a negative voltage is applied to a terminal 2 so that a negative bias voltage is applied to the gate (G).
FIG. 9 shows the transfer characteristic of the FET Q1. In FIG. 9, the horizontal axis indicates the gate voltage Vg, the vertical axis indicates the drain current I.sub.DS, and I.sub.DSS and V.sub.P represent the drain saturation current and the pinch-off voltage, respectively. In the case of performing class A amplification, a gate bias is set at point P1 in FIG. 9. More specifically, the gate voltage V.sub.g0 at point P1 of the FET Q1 is -1 V or thereabouts.
Referring again to FIG. 8, in order to set the gate voltage Vg of the FET Q1 at -1 V or thereabouts, a voltage of about -5 V is applied to the terminal 2 and is divided by resistors R1 and R2. A signal is input to a terminal 3 and output from a terminal 4. A low-pass filter constituted by an inductor L1 and a capacitor C1 and a low-pass filter constituted by an inductor L2 and a capacitor C2 each serve as a high-frequency suppressing circuit.
The GaAs FET constitutes a Schottky barrier gate, and since a reverse bias voltage is applied thereto, no gate current flows during small signal operation which is an operation of the GaAs FET upon the application of a signal having a small amplitude. However, when the GaAs FET is operated near the saturation output power with a large signal input thereto, current flows through the gate of the GaAs FET in both forward and reverse directions, as shown in FIG. 10. In the case where the GaAs FET is used to provide saturation output power of 10 watts or more, the gate current rises to about 10 mA. In the conventional gate bias circuit shown in FIG. 8, such gate current causes a voltage drop at the voltage dividing resistors R1 and R2; therefore, the gate voltage Vg of the FET Q1 and thus the drain current thereof undergo variations, causing variations of the output power.
Specifically, the forward gate current is the current flowing from the gate to the source of the FET Q1, and this current flows to the resistor R2, causing a voltage drop thereat. Consequently, the gate voltage Vg takes a large negative value (e.g., V.sub.g2) and causes a reduction (I.sub.DS1) of the drain current, as shown in FIG. 9, making it impossible to obtain predetermined output power.
The reverse gate current is the current flowing from the drain to the gate, and this current flows to the resistor R1, causing a voltage drop thereat. Consequently, the gate voltage Vg takes a small negative value (e.g., V.sub.g1), causing an increase (I.sub.DS2) of the drain current, as shown in FIG. 9. In a high-output GaAs FET, the quantity of heat generated thereby increases with increase in the drain current, and since the reverse gate current is associated with a positive temperature coefficient, the GaAs FET has the property that the reverse gate current increases with increase in the temperature of the GaAs FET. Accordingly, if reverse gate current flow occurs in the FET Q1, the drain current increases, as mentioned above, and thus the temperature of the FET Q1 rises, which in turn causes an increase of the reverse gate current. If this cycle is repeated, that is, if thermal runaway occurs, the FET Q1 may finally be broken due to increased temperature.
Thus, gate current flow in the GaAs FET causes variations of the gate voltage Vg, which results in variations of the output power and even the breakdown of the GaAs FET.